1. Field of the Invention
The present invention is directed to circuitry for protecting an MOS integrated circuit from destructive currents under reverse battery conditions.
2. Discussion of the Prior Art
FIGS. 1A and 1B illustrate a simple conventional, junction-isolation, N-well CMOS circuit with its associated PN junction diodes. In a reverse battery situation, e.g. when the batteries are inadvertently placed in an electronic device in reverse polarity, the normally-positive V.sub.DD supply pad becomes the negative supply and the normally-negative V.sub.SS supply pad becomes the positive supply. Under this condition, the diodes associated with the circuit are forward biased, the current from the battery through the circuit becomes very large and the circuit is destroyed.
FIG. 2 illustrates the same prior art circuit which is implemented utilizing P-well technology.
The conventional solution to the reverse battery problem is to provide either a large external resistor or an external diode in series with the V.sub.DD supply pad to prevent large currents from flowing through the circuit during reverse battery. However, use of these external devices creates a large voltage drop across the device during normal operation of the circuit. This complicates circuit design. Furthermore, integration of a protective resistor does not solve the voltage drop problem and integration of a protective diode creates parasitics within the circuit.